Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

Aspect-Ratio-Dependent Copper Electrodeposition Technique for Very High Aspect-Ratio Through-Hole Plating

Copper electrodeposition in high-aspect-ratio through-holes micromachined by deep reactive ion etching is one of the most essential processes for fabricating through-wafer interconnects, which will be used in developing future generation high-speed, compact 3D microelectronic devices. Although copper electrodeposition is a well-established process, completely void-free electroplating in very de...

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect...

Tailoring femtosecond 1.5-μm Bessel beams for manufacturing high-aspect-ratio through-silicon vias

Three-dimensional integrated circuits (3D ICs) are an attractive replacement for conventional 2D ICs as high-performance, low-power-consumption, and small-footprint microelectronic devices. However, one of the major remaining challenges is the manufacture of high-aspect-ratio through-silicon vias (TSVs), which is a crucial technology for the assembly of 3D Si ICs. Here, we present the fabricati...

Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

0026-2714/$ see front matter 2012 Elsevier Ltd. A http://dx.doi.org/10.1016/j.microrel.2012.06.140 ⇑ Corresponding author. E-mail address: [email protected] Through-silicon vias (TSVs), being one of the key enabling technologies for three dimensional (3D) integrated circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremend...